package hardcaml

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package hardcaml
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Library
Module
Module type
Parameter
Class
Class type

Design

module Always : sig ... end

Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

module Assertions : sig ... end

Assertions within Hardcaml simulations.

module Caller_id : sig ... end

Optionally embed the callstack in the signal type when it is created.

module Comb : sig ... end

Combinational logic API.

module Constant : sig ... end

Representation of variable width Constants and conversion to/from OCaml types.

module Interface : sig ... end

Interfaces specify the widths and names of a group of signals, and some functions for manipulating the signals as a group.

module Instantiation : sig ... end

Instantiation of sub-modules.

module Parameter : sig ... end

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

module Parameter_name : sig ... end

RTL name of parameters on instantiated modules.

module Property : sig ... end
module Property_manager : sig ... end
module Reg_spec : sig ... end
module Scope : sig ... end

Scopes control the process of hierarchical circuit generation.

module Signal : sig ... end

Hardware design datatype suitable for simulation and netlist generation

module Structural : sig ... end

Hardware generation API that includes tri-states - used for toplevel module generation.

Circuits

module Circuit : sig ... end

Creation and manipulation of hardware circuits

module Circuit_database : sig ... end

A database which holds a collection of circuits, indexed by a unique circuit name.

module Circuit_utilization : sig ... end

Utilization information for a circuit which can be printed to a sexp.

module Hierarchy : sig ... end

Allow a hardcaml circuit to be defined as a hierarchy of modules, rather than just a single flat module.

module Mangler : sig ... end

Map a set of names to a set of unique names.

Simulation and modelling

module Bits : sig ... end

An immutable finite sequence of bits with a specified width.

module Bits_list : sig ... end

Combinational logic described as lists of Bits ie 0;1;1;1;0.

module Combinational_op : sig ... end

A custom combinational operation that can be inserted into a simulation.

module Combinational_ops_database : sig ... end

A database which holds a collecton of custom combinational operations for use with Cyclesim based simulators.

module Cyclesim : sig ... end

Cycle accurate simulator

module Cyclesim_float_ops : sig ... end

Floating point operations for simulation.

module Logic : sig ... end
module Vcd : sig ... end

VCD (Verilog Change Dump) generation utilities, and a Cyclesim wrapper function.

module Wave_format : sig ... end

How to display the value of a signal. Generally used in waveforms.

module Wave_data : sig ... end

Rtl generation

module Rtl : sig ... end
module Rtl_attribute : sig ... end

RTL attribute specification. Only relevant to downstream tooling.

module Reserved_words : sig ... end

Tables of reserved words in Verilog, VHDL and OCaml.

Transformations and passes

module Design_rule_checks : sig ... end

Simple circuit analsysis passes for common issues.

module Dedup : sig ... end

Deduplicates combinatorial nodes performing redundant computation.

module Signal_graph : sig ... end

A Signal_graph.t is a created from a list of signals, and defined by tracing back to inputs (unassigned wires or constants). Functions are provided for traversing the graph.

Misc types

module Architecture : sig ... end

Hardware architecture specification.

module Build_mode : sig ... end

Specify whether to configure the hardware for simulation or synthesis.

module Edge : sig ... end

Specification of rising or falling edge of a signal (normally a clock).

module Enum : sig ... end

The Enum contains functors that can be used to create special interface modules to represent an enumeration type (ie: a variant with no arguments).

module Flags_vector : sig ... end
module Level : sig ... end

Specification of a signals level - high or low.

module Read_port : sig ... end

A memory read port.

module Side : sig ... end

Used to specify when an operation should be performed - before or after an event like a clock edge.

module Signedness : sig ... end
module Types : sig ... end
module With_valid : sig ... end
module Write_port : sig ... end

A memory write port.

Core circuits

module Async_fifo : sig ... end

Simple and fast distributed RAM based asynchronous FIFO. The depth of the FIFO is parameterizable, however, it should be less than or equal to 2 ^ LUT_SIZE to avoid glitches on the addressing logic.

module Fifo : sig ... end

Synchronous FIFO implementions with optional showahead functionality and pipelining stages.

module Ram : sig ... end

Random access memories described using RTL inference.

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