package hardcaml

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package hardcaml
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type t = {
  1. is_internal_port : (Signal.t -> Base.bool) Base.option;
    (*

    Passed each signal in the design which has a name. Returns true if the simulator should expose it for reading in the testbench (or display in a waveform).

    *)
  2. combinational_ops_database : Combinational_ops_database.t;
    (*

    Database of instantiations which may be replace by a combinational operation.

    *)
  3. deduplicate_signals : Base.bool;
    (*

    Perform a pass which finds structurally equal signals and shares them.

    *)
  4. store_circuit : Base.bool;
    (*

    Stores the post-processed circuit that is used to compile the simulation. This should generally be set to false, so that the Circuit can be garbage collected once the simulation is constructed.

    *)
}
val default : t
val trace : [ `Everything | `All_named | `Ports_only ] -> t
val trace_all : t
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