package hardcaml

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package hardcaml
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Module Hardcaml.VcdSource

VCD (Verilog Change Dump) generation utilities, and a Cyclesim wrapper function.

This deals with the gory details of the format, but external code is expected to manage the generation of data values and properly detect they are the same and should not be included.

To generate a vcd;

  - build the variables and scopes, and assocaite data generators with variables
  - write_header
  - iteratate, while outputting changed values:
    - write_time
    - Var.write...
    - Var.write...
    - ...
Sourcemodule Timescale : sig ... end

Timescales.

Sourcemodule Var : sig ... end

Var declarations within the vcd. They make a name to a unique (short) identifier used in the VCD data section.

Sourcemodule Scope : sig ... end

Scopes define the hierarchical relationships of Var.ts

Sourcemodule Config : sig ... end

VCD header configuration and timescale.

Sourceval write_header : Stdio.Out_channel.t -> config:Config.t -> scopes:Scope.t Base.list -> Base.unit

Write out the vcd header.

Write a time in the data portion. Should be followed by data values.

Sourceval wrap : Stdio.Out_channel.t -> ('i, 'o) Cyclesim.t -> ('i, 'o) Cyclesim.t

wrap a Cyclesim simulator to generate a vcd file.

Flush the out channel!

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