package hardcaml

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package hardcaml
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VCD (Verilog Change Dump) generation utilities, and a Cyclesim wrapper function.

This deals with the gory details of the format, but external code is expected to manage the generation of data values and properly detect they are the same and should not be included.

To generate a vcd;

      - build the variables and scopes, and assocaite data generators with variables
      - write_header
      - iteratate, while outputting changed values:
        - write_time
        - Var.write...
        - Var.write...
        - ...
module Timescale : sig ... end

Timescales.

module Var : sig ... end

Var declarations within the vcd. They make a name to a unique (short) identifier used in the VCD data section.

module Scope : sig ... end

Scopes define the hierarchical relationships of Var.ts

module Config : sig ... end

VCD header configuration and timescale.

val write_header : Stdio.Out_channel.t -> config:Config.t -> scopes:Scope.t Base.list -> Base.unit

Write out the vcd header.

val write_time : Stdio.Out_channel.t -> Base.int -> Base.unit

Write a time in the data portion. Should be followed by data values.

val wrap : Stdio.Out_channel.t -> ('i, 'o) Cyclesim.t -> ('i, 'o) Cyclesim.t

wrap a Cyclesim simulator to generate a vcd file.

Flush the out channel!

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