package hardcaml

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package hardcaml
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type 'a t = {
  1. current : Signal.t;
  2. is : 'a -> Signal.t;
  3. set_next : 'a -> always;
    (*

    switch cases does a switch on all possible states. The cases must be exhaustive and irredundant. If the cases are non-exhaustive, one can supply ~default to make them exhaustive.

    *)
  4. switch : ?default:always Base.list -> 'a cases -> always;
}
val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
module Encoding : sig ... end
module type State = sig ... end
val create : ?encoding:Encoding.t -> ?auto_wave_format:Base.bool -> ?enable:Signal.t -> (module State with type t = 'a) -> Reg_spec.t -> 'a t

create reg_spec ~e creates a new state machine where the state is stored in a register created from reg_spec and e.

encoding chooses the state encoding from binary, gray or onehot. Generally binary is correctly identified by synthesizers and transformed to onehot.

auto_wave_format will automatically make state names show in waveforms.

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