package hardcaml

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package hardcaml
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Control of name generation in a hierarchy of modules. The position of a module within a hierarchy is determined by a path which leads back to the (single) top most parent module. Signal names may be pre-pended with some representation of that path.

  • No_path - Nothing is added to the name.
  • Local_path - Only the name of the enclosing module is added to the name.
  • Full_path - The full path is included in the name
  • Auto - The full path is tracked in the scope, but names have no path.

Generally hierarchical names are taken from the circuit name, though it is possible to specify a different instantiation name. These names are mangled so they are unique within each scope.

Auto mode works in conjunction with the Hierarchy module to automatically rewrite names with full paths without having to work with explicit path names.

type t =
  1. | Auto
  2. | Full_path
  3. | Local_path
  4. | No_path
include Ppx_compare_lib.Equal.S with type t := t
val equal : t -> t -> bool
val sexp_of_t : t -> Sexplib0.Sexp.t
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