package hardcaml

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package hardcaml
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A Signal_graph.t is a created from a list of signals, and defined by tracing back to inputs (unassigned wires or constants). Functions are provided for traversing the graph.

When traversing using depth_first_seach we can specify upto which means the search will stop when it reaches any signal in the given list (which is also /not/ included as part of the search).

type t
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : ?upto:Signal.t Base.list -> Signal.t Base.list -> t

Create a Signal_graph.t from a list of signals (commonly, circuit outputs).

Traverse the graph and find all inputs. Badly formed inputs (no name, or multiple names) return an error.

val outputs : ?validate:Base.bool -> t -> Signal.t Base.list Base.Or_error.t

Return the outputs of the signal graph. If validate is true, then the outputs are checked for compatibility with circuit outputs.

Visit all signals in the graph, starting at the outputs, in a depth-first manner. Each signal is visited only once. f_before is called before recursing on each signal's fan-in. Similiarly, f_after is called after recursing on the fan-in.

If deps is provided it will be used to compute signal dependencies rather than the default definition. This is useful for terminating traversals based on some condition on signals, e.g., if it's a register or a memory.

val fold : t -> init:'a -> f:('a -> Signal.t -> 'a) -> 'a

Fold across all signals in the graph, starting at the outputs. Each signal is visited only once.

val filter : t -> f:(Signal.t -> Base.bool) -> Signal.t Base.list

Return a list of all signals in the graph for whom f signal returns true.

val iter : t -> f:(Signal.t -> Base.unit) -> Base.unit

Iterate over all signals in the graph.

val detect_combinational_loops : t -> Base.unit Base.Or_error.t

Retuns an error if the graph has a combinational loop, that is, a path from a signal back to itself that doesn't pass though a register, memory or instantiation.

val normalize_uids : t -> t

normalize_uids t creates a copy of t that is identical to t except the uids are numbered starting at 1.

val fan_out_map : t -> Hardcaml__.Signal.Type.Uid_set.t Base.Map.M(Hardcaml__.Signal.Uid).t

Fan-out of each signal in the signal graph. The fan-out of a signal is the set of signals it drives.

val fan_in_map : t -> Hardcaml__.Signal.Type.Uid_set.t Base.Map.M(Hardcaml__.Signal.Uid).t

Fan-in of each signal in the signal graph. The fan-in of a signal is the set of signals that drive it.

val topological_sort : deps:(module Hardcaml__.Signal.Type.Deps) -> t -> (Signal.t Base.list, Signal.t Base.list) Base.Result.t

topological_sort t sorts the signals in t so that all the signals in deps s occur before s.

val topological_sort_exn : deps:(module Hardcaml__.Signal.Type.Deps) -> t -> Signal.t Base.list
module Deps_for_simulation_scheduling : sig ... end

Signal dependencies used for simulation scheduling. Breaks loops through sequential elements like registers and memories.

module Deps_for_loop_checking : sig ... end

Like Deps_for_simulation_scheduling, except loops are allowed through instantiations.

val last_layer_of_nodes : is_input:(Signal.t -> Base.bool) -> t -> Hardcaml__.Signal.Uid.t Base.List.t

Final layer of combinational nodes which sit on the path between the outputs and any driving register or memory.

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