package hardcaml

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package hardcaml
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Allow a hardcaml circuit to be defined as a hierarchy of modules, rather than just a single flat module.

val hierarchical : (module Interface.S_Of_signal with type Of_signal.t = 'i) -> (module Interface.S_Of_signal with type Of_signal.t = 'o) -> ?config:Circuit.Config.t -> ?instance:Base.string -> ?attributes:Rtl_attribute.t Base.list -> scope:Scope.t -> name:Base.string -> (Scope.t -> 'i -> 'o) -> 'i -> 'o
val fold : Circuit.t -> Circuit_database.t -> init:'a -> f: ('a -> Circuit.t Base.option -> Hardcaml__.Signal.Type.instantiation Base.option -> 'a) -> 'a

Fold through every circuit and instantiation in a hierarchical design.

f will be passed the corresponding circuit if it exists in the database, and a Signal.instanation specification, unless the top most module.

val print : Circuit.t -> Circuit_database.t -> Base.unit
module With_interface (I : Interface.S) (O : Interface.S) : sig ... end
module In_scope (I : Interface.S) (O : Interface.S) : sig ... end

Support for hierarchically structured Hardcaml designs. We extend the standard Interface.Create_fn pattern so that the create function also takes a Scope.t argument. This allows scoping of signal names and automatic recording of the design in a Circuit_database.t.

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