package hardcaml

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package hardcaml
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type range =
  1. | Vector of {
    1. width : Base.int;
    }
  2. | Bit
val equal_range : range -> range -> Base.bool
val sexp_of_range : range -> Sexplib0.Sexp.t
type reg_or_wire =
  1. | Reg
  2. | Wire
val equal_reg_or_wire : reg_or_wire -> reg_or_wire -> Base.bool
val sexp_of_reg_or_wire : reg_or_wire -> Sexplib0.Sexp.t
type var = {
  1. name : Base.string;
  2. range : range;
  3. reg_or_wire : reg_or_wire;
  4. attributes : Rtl_attribute.t Base.list;
  5. comment : Base.string Base.option;
}
val equal_var : var -> var -> Base.bool
val sexp_of_var : var -> Sexplib0.Sexp.t
type output = {
  1. output : var;
  2. driven_by : var Base.option;
}
val sexp_of_output : output -> Sexplib0.Sexp.t
type logic_declaration = {
  1. read : var;
  2. write : var;
  3. all_names : var Base.list;
}
val sexp_of_logic_declaration : logic_declaration -> Sexplib0.Sexp.t
type multiport_memory_declaration = {
  1. memory : var;
  2. memory_type : Base.string;
  3. depth : Base.int;
  4. range : range;
}
val sexp_of_multiport_memory_declaration : multiport_memory_declaration -> Sexplib0.Sexp.t
type declaration =
  1. | Logic of logic_declaration
  2. | Multiport_memory of multiport_memory_declaration
  3. | Inst of logic_declaration
val sexp_of_declaration : declaration -> Sexplib0.Sexp.t
type binop =
  1. | Add
  2. | Sub
  3. | Mulu
  4. | Muls
  5. | And
  6. | Or
  7. | Xor
  8. | Eq
  9. | Lt
val sexp_of_binop : binop -> Sexplib0.Sexp.t
type assignment =
  1. | Binop of {
    1. lhs : var;
    2. arg_a : var;
    3. op : binop;
    4. arg_b : var;
    5. signed : Base.bool;
    }
  2. | Not of {
    1. lhs : var;
    2. arg : var;
    }
  3. | Mux of {
    1. lhs : var;
    2. select : var;
    3. cases : var Base.list;
    }
  4. | Select of {
    1. lhs : var;
    2. arg : var;
    3. high : Base.int;
    4. low : Base.int;
    }
  5. | Concat of {
    1. lhs : var;
    2. args : var Base.list;
    }
  6. | Const of {
    1. lhs : var;
    2. constant : Bits.t;
    }
  7. | Wire of {
    1. lhs : var;
    2. driver : var;
    }
val sexp_of_assignment : assignment -> Sexplib0.Sexp.t
type condition =
  1. | Level of {
    1. level : Level.t;
    2. var : var;
    }
  2. | Edge of {
    1. edge : Edge.t;
    2. var : var;
    }
  3. | Clock of {
    1. edge : Edge.t;
    2. clock : var;
    }
val sexp_of_condition : condition -> Sexplib0.Sexp.t
type always =
  1. | If of {
    1. condition : condition;
    2. on_true : always Base.list;
    3. on_false : always Base.list;
    }
  2. | Assignment of {
    1. lhs : var;
    2. rhs : var;
    }
  3. | Memory_assignment of {
    1. lhs : var;
    2. index : var;
    3. rhs : var;
    }
  4. | Case of {
    1. select : var;
    2. cases : always Base.list Base.list;
    }
val sexp_of_always : always -> Sexplib0.Sexp.t
type sensitivity = {
  1. edge : Edge.t;
  2. var : var;
}
val sexp_of_sensitivity : sensitivity -> Sexplib0.Sexp.t
type sensitivity_list =
  1. | Star
  2. | Edges of sensitivity Base.list
val sexp_of_sensitivity_list : sensitivity_list -> Sexplib0.Sexp.t
type instantiation_input_port = {
  1. port_name : Base.string;
  2. connection : var;
}
val sexp_of_instantiation_input_port : instantiation_input_port -> Sexplib0.Sexp.t
type instantiation_output_port = {
  1. port_name : Base.string;
  2. connection : var;
  3. high : Base.int;
  4. low : Base.int;
}
val sexp_of_instantiation_output_port : instantiation_output_port -> Sexplib0.Sexp.t
type instantiation = {
  1. name : Base.string;
  2. instance : Base.string;
  3. parameters : Parameter.t Base.list;
  4. input_ports : instantiation_input_port Base.list;
  5. output_ports : instantiation_output_port Base.list;
  6. attributes : Rtl_attribute.t Base.list;
}
val sexp_of_instantiation : instantiation -> Sexplib0.Sexp.t
type statement =
  1. | Assignment of assignment
  2. | Instantiation of instantiation
  3. | Always of {
    1. sensitivity_list : sensitivity_list;
    2. always : always;
    }
  4. | Mux of {
    1. to_assignment : Base.unit -> statement;
    2. to_always : Base.unit -> statement;
    3. is_mux2 : Base.bool;
    }
  5. | Multiport_mem of {
    1. always : statement Base.array;
    }
  6. | Mem_read_port of {
    1. lhs : var;
    2. memory : var;
    3. address : var;
    }
val sexp_of_statement : statement -> Sexplib0.Sexp.t
type t = {
  1. name : Base.string;
  2. inputs : var Base.list;
  3. outputs : output Base.list;
  4. declarations : declaration Base.list;
  5. statements : statement Base.list;
  6. var_map : declaration Base.Map.M(Hardcaml__.Signal.Uid).t;
    (*

    Map all input, output and internal signals to a var declaration

    *)
}
val sexp_of_t : t -> Sexplib0.Sexp.t
val of_circuit : blackbox:Base.bool -> Hardcaml__.Rtl_name.t -> Circuit.t -> t
module Signals_name_map : sig ... end

Map signal names to mangled RTL names. This used in Hardcaml_verilator.

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