package hardcaml

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Module Rtl.Signals_name_mapSource

Map signal names to mangled RTL names. This used in Hardcaml_verilator.

Sourcemodule Uid_with_index : sig ... end
Sourcetype t_rtl_ast
include Ppx_compare_lib.Equal.S with type t := t
Sourceval equal : t -> t -> bool
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
Sourceval create : t_rtl_ast -> t
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