package hardcaml

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package hardcaml
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Hardware generation API that includes tri-states - used for toplevel module generation.

The API is very similar to Signal except for instantiation which is done differently.

type name = string
type id = int
type width = int
type signal =
  1. | Empty
  2. | Module_input of id * name * width * Rtl_attribute.t list Stdlib.ref
  3. | Module_output of id * name * width * signal Stdlib.ref * Rtl_attribute.t list Stdlib.ref
  4. | Module_tristate of id * name * width * signal list Stdlib.ref * Rtl_attribute.t list Stdlib.ref
  5. | Internal_wire of id * width * signal Stdlib.ref
  6. | Internal_triwire of id * width * signal list Stdlib.ref
  7. | Instantiation_output of id * name
    (*

    reference to instantiation

    *)
  8. | Instantiation_tristate of id * name
  9. | Instantiation of id * name * (string * generic) list * (string * signal) list * (string * signal) list * (string * signal) list * string option * Rtl_attribute.t list
  10. | Rtl_op of id * width * rtl_op
and rtl_op =
  1. | Constant of string
  2. | Select of int * int * signal
  3. | Concat of signal list
  4. | Mux of signal * signal list
and generic =
  1. | GInt of int
  2. | GFloat of float
  3. | GString of string
  4. | GUnquoted of string
type circuit = {
  1. name : string;
  2. id : id;
  3. mutable signals : signal list;
}
exception Invalid_submodule_input_connection of string * string * signal
exception Invalid_submodule_output_connection of string * string * signal
exception Invalid_submodule_tristate_connection of string * string * signal
exception Wire_already_assigned of signal
exception Invalid_assignment_target of signal
exception Cant_assign_wire_with of signal
exception Cant_assign_triwire_with of signal
exception Invalid_name of signal
exception Invalid_width of signal
exception Invalid_id of signal
exception Invalid_constant of string
exception Rtl_op_arg_not_readable of signal
exception Too_few_mux_data_elements
exception Too_many_mux_data_elements of int
exception All_mux_data_elements_must_be_same_width of int list
exception No_elements_to_concat
exception Select_index_error of int * int
exception Binop_arg_widths_different of string
exception No_circuit
exception Circuit_already_started
val reset_circuit_database : unit -> unit

Clears the circuit database and resets all internal state back to initial values.

val start_circuit : string -> unit

start circuit

val end_circuit : unit -> unit

complete circuit, add to database

val find_circuit : string -> circuit

find circuit in database

val create_circuit : string -> (unit -> unit) -> circuit
val add_attribute : signal -> Rtl_attribute.t -> unit

Add an attribute to the signal. Currently only works on input and outputs.

val width : signal -> int
val mk_input : string -> int -> signal
val mk_output : string -> int -> signal
val mk_tristate : string -> int -> signal
val mk_wire : int -> signal
val mk_triwire : int -> signal
val (<==) : signal -> signal -> unit
val is_connected : signal -> bool
val inst : ?instance_name:string -> ?attributes:Rtl_attribute.t list -> ?g:(string * generic) list -> ?i:(string * signal) list -> ?o:(string * signal) list -> ?t:(string * signal) list -> string -> unit
val (==>) : 'a -> 'b -> 'a * 'b
val of_bit_string : string -> signal
val z : int -> signal
val mux : signal -> signal list -> signal
val concat_msb : signal list -> signal
val select : signal -> int -> int -> signal
module type Config = sig ... end
val prefix : string
module Base (C : Config) : Comb.Primitives with type t = signal

the comb API must be (rebuilt) between each circuit

module Base0 : Comb.Primitives with type t = signal

progressively more structural APIs

module Base1 : Comb.Primitives with type t = signal

includes mux, concat, select

module Base2 : Comb.Primitives with type t = signal

includes consts

val write_verilog : (string -> unit) -> circuit -> unit
module Lib : sig ... end
module With_interface (I : Interface.S) (O : Interface.S) (T : Interface.S) : sig ... end
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