package hardcaml

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package hardcaml

hardcaml
- Hardcaml
  - Always
    
    State_machine
    
    Encoding
    
    State
    
    Variable
  - Architecture
  - Assertions
    
    Always
    
    Violated_or_not
  - Async_fifo
    
    Make
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    M
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    S
  - Bits
    
    Expert
    
    Mutable
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Bits_list
    
    Bool_comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Int_comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Make
    
    Signed
    
    Sop
    
    T
    
    Typed_math
    
    Unsigned
    
    Uop
    
    T
    
    X
    
    X_comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Build_mode
  - Caller_id
    
    Mode
  - Circuit
    
    Config
    
    Port_checks
    
    Signal_map
    
    With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Circuit_database
  - Circuit_utilization
  - Comb
    
    Gates
    
    Make
    
    Primitives
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Make_primitives
    
    Gates
    
    Primitives
    
    S
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Combinational_op
  - Combinational_ops_database
  - Constant
    
    Bit
    
    Expert
    
    Make_bit_list
    
    Bit
    
    Raw
  - Cyclesim
    
    Combine_error
    
    Config
    
    Memory
    
    Node
    
    Port_list
    
    Private
    
    Step
    
    Traced_nodes
    
    Reg
    
    Traced
    
    With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Cyclesim_float_ops
    
    Double
    
    Float
    
    Real
  - Dedup
  - Design_rule_checks
  - Edge
  - Enum
    
    Make_binary
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Cases
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    Make_enums
    
    Binary
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    Cases
    
    One_hot
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    Make_one_hot
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Cases
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    S_enum
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Cases
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    S_enums
    
    Binary
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    Cases
    
    One_hot
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    X
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
  - Fifo
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Config
    
    Kinded_fifo
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    With_interface
    
    Config
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Flags_vector
    
    Cases
    
    Make
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Cases
    
    Comb
    
    Flags
    
    Map
    
    Diff
    
    Key
    
    Provide_bin_io
    
    Key
    
    Provide_hash
    
    Key
    
    Provide_of_sexp
    
    Key
    
    Replace_polymorphic_compare
    
    Set
    
    Diff
    
    Elt
    
    Provide_bin_io
    
    Elt
    
    Provide_hash
    
    Elt
    
    Provide_of_sexp
    
    Elt
    
    Unstable
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
    
    S
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Flags
    
    Map
    
    Diff
    
    Key
    
    Provide_bin_io
    
    Key
    
    Provide_hash
    
    Key
    
    Provide_of_sexp
    
    Key
    
    Replace_polymorphic_compare
    
    Set
    
    Diff
    
    Elt
    
    Provide_bin_io
    
    Elt
    
    Provide_hash
    
    Elt
    
    Provide_of_sexp
    
    Elt
    
    Unstable
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe
    
    Unsafe_assoc_by_port_name
  - Hierarchy
    
    In_scope
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Instantiation
    
    Expert
    
    With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Interface
    
    Ast
    
    Ast
    
    Field
    
    Sequence
    
    Kind
    
    Type
    
    Create_fn
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    Empty
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    Make
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    X
    
    Make_interface_with_conversion
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    M
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Repr
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    Unsafe_assoc_by_port_name
    
    Pre
    
    Pre_partial
    
    S
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    S_Of_signal
    
    Names_and_widths
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    S_with_ast
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    Update
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    M
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Pre
    
    Unsafe_assoc_by_port_name
  - Level
  - Logic
    
    Bit_vector
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Four_state
    
    Variants
    
    Four_state_vector
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Std_logic
    
    Variants
    
    Std_logic_vector
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
  - Mangler
  - Parameter
    
    Value
    
    Variants
  - Parameter_name
  - Property
    
    CTL
    
    LTL
  - Property_manager
  - Ram
    
    Collision_mode
  - Read_port
  - Reg_spec
  - Reserved_words
  - Rtl
    
    Ast
    
    Signals_name_map
    
    Uid_with_index
    
    Blackbox
    
    Deprecated
    
    Uid_with_index
    
    Verilog
    
    VerilogNames
    
    Vhdl
    
    VhdlNames
    
    Digest
    
    Expert
    
    Language
    
    Name
    
    Language
    
    Verilog
    
    Vhdl
    
    Output_mode
    
    Signals_name_map
    
    Uid_with_index
    
    Verilog
    
    Vhdl
  - Rtl_attribute
    
    Value
    
    Vivado
    
    Ram_style
    
    Srl_style
  - Scope
    
    Naming_scheme
    
    Path
  - Side
  - Signal
    
    Signed
    
    Sop
    
    Typed_math
    
    Unoptimized
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Unsigned
    
    Uop
  - Signal_graph
  - Signedness
  - Structural
    
    Base
    
    C
    
    Base0
    
    Base1
    
    Base2
    
    Config
    
    Lib
    
    With_interface
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    T
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
  - Types
    
    Arg_with_length
    
    Array
    
    A
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
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  - Vcd
    
    Config
    
    Scope
    
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  - Wave_format
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  - Write_port

Legend:
Library
Module
Module type
Parameter
Class
Class type

module type Std_logic = sig ... end

module type Four_state = sig ... end

module Std_logic : Std_logic

module Four_state : Four_state

module Std_logic_vector : Bits_list.Comb with type t = Std_logic.t Base.list

module Bit_vector : Bits_list.Comb with type t = Base.int Base.list

module Four_state_vector : Bits_list.Comb with type t = Four_state.t Base.list