package hardcaml

  1. Overview
  2. Docs
package hardcaml
Legend:
Page
Library
Module
Module type
Parameter
Class
Class type
Source

Module Rtl_attribute.VivadoSource

A collection of common Xilinx Vivado attributes.

Sourceval async_reg : bool -> t

Inform Vivado that a registers data input is asychronous to it's clock.

Sourceval dont_touch : bool -> t

Instruct the synthesizer and place & route tools to keep the node. Cannot be applied to a port.

Sourceval keep_hierarchy : bool -> t

Setting keep_hierarchy to yes will prevent Vivado from optimizating across module boundaries. Can only be applied to modules or instances.

Sourceval fsm_encoding : [ `auto | `gray | `johnson | `none | `one_hot | `sequential ] -> t

Select encoding of finite state machine. Apply to state register.

Sourceval mark_debug : bool -> t

Export net for debugging with chipscope.

Sourceval keep : bool -> t

Similar to dont_touch

Sourceval io_buffer_type : [ `IBUF | `OBUF | `None ] -> t

io_buffer_type Vivado attribute. Applied to top level ports and instructs Vivado not to infer the buffer type, instead using the attribute below.

Sourcemodule Ram_style : sig ... end
Sourcemodule Srl_style : sig ... end

SRL_STYLE instructs the synthesis tool on how to infer SRLs that are found in the design. Accepted values are