package hardcaml

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package hardcaml
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Synchronous FIFO implementions with optional showahead functionality and pipelining stages.

type 'a t = {
  1. q : 'a;
  2. full : 'a;
  3. empty : 'a;
  4. nearly_full : 'a;
  5. nearly_empty : 'a;
  6. used : 'a;
  7. rd_rst_busy : 'a;
  8. wr_rst_busy : 'a;
}
include sig ... end
val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
val iter : 'a t -> f:('a -> Base.unit) -> Base.unit
val iter2 : 'a t -> 'b t -> f:('a -> 'b -> Base.unit) -> Base.unit
val map : 'a t -> f:('a -> 'b) -> 'b t
val map2 : 'a t -> 'b t -> f:('a -> 'b -> 'c) -> 'c t
val to_list : 'a t -> 'a Base.list
val port_names_and_widths : (Base.string * Base.int) t
val equal : 'a Base__Equal.equal -> 'a t Base__Equal.equal
val port_names : Base.string t
val port_widths : Base.int t
val const : 'a -> 'a t
type tag
val tags : tag t
val to_alist : 'a t -> (tag * 'a) Base.list
val of_alist : (tag * 'a) Base.list -> 'a t
val sum_of_port_widths : Base.int
module Unsafe_assoc_by_port_name : sig ... end
val zip : 'a t -> 'b t -> ('a * 'b) t
val zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t
val zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t
val zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t
val map3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> 'd) -> 'd t
val map4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> 'e) -> 'e t
val map5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> 'f) -> 'f t
val iter3 : 'a t -> 'b t -> 'c t -> f:('a -> 'b -> 'c -> Base.unit) -> Base.unit
val iter4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> 'b -> 'c -> 'd -> Base.unit) -> Base.unit
val iter5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f:('a -> 'b -> 'c -> 'd -> 'e -> Base.unit) -> Base.unit
val fold : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc) -> 'acc
val fold2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc) -> 'acc
val scan : 'a t -> init:'acc -> f:('acc -> 'a -> 'acc * 'b) -> 'b t
val scan2 : 'a t -> 'b t -> init:'acc -> f:('acc -> 'a -> 'b -> 'acc * 'c) -> 'c t
val offsets : ?rev:Base.bool -> Base.unit -> Base.int t
val of_interface_list : 'a t Base.list -> 'a Base.list t
val to_interface_list : 'a Base.list t -> 'a t Base.list
module All (M : Base.Monad.S) : sig ... end
val or_error_all : 'a Base.Or_error.t t -> 'a t Base.Or_error.t
module type Comb = sig ... end
module Make_comb (Comb : Comb.S) : sig ... end
module Of_bits : sig ... end
module Of_signal : sig ... end
module Of_always : sig ... end
module Names_and_widths : sig ... end
type 'a create_params = ?nearly_empty:Base.int -> ?nearly_full:Base.int -> ?overflow_check:Base.bool -> ?reset:Signal.t -> ?underflow_check:Base.bool -> ?ram_attributes:Rtl_attribute.t Base.list -> ?scope:Scope.t -> 'a
type create_fifo = (Base.unit -> capacity:Base.int -> clock:Signal.t -> clear:Signal.t -> wr:Signal.t -> d:Signal.t -> rd:Signal.t -> Signal.t t) create_params
module Kinded_fifo : sig ... end
Base RTL FIFO
val create : ?read_latency:Base.int -> ?showahead:Base.bool -> ?nearly_empty:Base.int -> ?nearly_full:Base.int -> ?overflow_check:Base.bool -> ?reset:Signal.t -> ?underflow_check:Base.bool -> ?ram_attributes:Rtl_attribute.t Base.list -> ?scope:Scope.t -> Base.unit -> capacity:Base.int -> clock:Signal.t -> clear:Signal.t -> wr:Signal.t -> d:Signal.t -> rd:Signal.t -> Signal.t Hardcaml__.Fifo_intf.T.t

create ~clock ~clear ~wr ~d ~rd capacity builds a FIFO with capacity elements which is written with d when wr is high and read when rd is high.

The default reset configuration is to use a synchronous clr signal. An asynchronous rst may be optionally provided. One of clr or rst must be non-empty.

Optional overflow and underflow checking may be used. Data will not be written(/read) when the fifo is full(/empty) regardles or the wr/(rd) signals.

nearly_emtpy and nearly_full may be programmed to go high when the fifo is nearing an underflow or overflow state.

The showahead mode changes the read behaviour of the FIFO. When showahead is false read data is available 1 cycle after rd is high. With showahead true the data is available when the fifo is not empty (you can also think of this as data being available on the same cycle that rd is asserted). To support showahead behaviour the timing of the full/empty flag changes (although they still correctly indicate when it is safe to read or write to the FIFO). showahead mode has some extra cost in terms of extra logic. The implementation ensures the output is registered and timing performance is good - nearly as fast as the underlying RAM allows.

Note; showahead is sometimes referred to as "first word fall through". It uses the write-before-read ram mode which is problematic in synthesis so we include special logic that performs collision detection.

The used output indicates the number of elements currently in the FIFO.

read_latency can be assigned to insert pipelining on the output of the FIFO to improve timing.

Functions to derive fifo architectures from other architecetures.

val showahead_fifo_of_classic_fifo : Kinded_fifo.create_classic -> Kinded_fifo.create_showahead Base.Staged.t

Derived FIFO architectures.

val create_classic_with_extra_reg : ?nearly_empty:Base.int -> ?nearly_full:Base.int -> ?overflow_check:Base.bool -> ?reset:Signal.t -> ?underflow_check:Base.bool -> ?ram_attributes:Rtl_attribute.t Base.list -> ?scope:Scope.t -> Base.unit -> capacity:Base.int -> clock:Signal.t -> clear:Signal.t -> wr:Signal.t -> d:Signal.t -> rd:Signal.t -> Signal.t Hardcaml__.Fifo_intf.T.t

Adds an extra output register to the non-showahead fifo. This delays the output, but ensures there is no logic data on the fifo output. Adds an extra cycle of latency (2 cycles from write to empty low).

val create_showahead_from_classic : create_fifo

Constructs a showahead fifo from a non-showahead fifo. Only modifies the control flags. Has 2 cycles of latency.

val create_showahead_with_extra_reg : create_fifo

Constructs a fifo similarly to create_showahead_from_classic and ensures the output data is registered. Has 3 cycles of latency, but is slightly faster than create ~showahead:true - it seems to only be limited by the underlying RAM frequency.

val create_showahead_with_read_latency : read_latency:Base.int -> create_fifo

Creates a FIFO where read_latency is used to add pipelining to the output and improve timing, but exposes FIFO data as if operating in showahead mode which is convenient for interface with AXI streams.

Latency on this FIFO will be read_latency+1 cycles per read, but allows use of much larger FIFOs.

module type Config = sig ... end
module With_interface (Config : Config) : sig ... end

Create FIFO using interfaces.

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