package hardcaml

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package hardcaml
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Map signal names to mangled RTL names. This used in Hardcaml_verilator.

module Uid_with_index : sig ... end
type t_rtl_ast = t
include Ppx_compare_lib.Equal.S with type t := t
val equal : t -> t -> bool
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : t_rtl_ast -> t
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