package hardcaml

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Library
Module
Module type
Parameter
Class
Class type

Parameters

module M : S

Signature

module I : sig ... end
module O : sig ... end
val hierarchical : ?name:string -> ?use_negedge_sync_chain:bool -> ?sync_stages:int -> Scope.t -> Signal.t I.t -> Signal.t O.t
val create : ?use_negedge_sync_chain:bool -> ?sync_stages:int -> ?scope:Scope.t -> Signal.t I.t -> Signal.t O.t
val create_with_delay : ?delay:Stdlib.Int.t -> Scope.t -> Signal.t I.t -> Signal.t O.t

Create an async FIFO that O.valid goes high after delay clocks of a o.valid low start. This is useful for packet buffering across clock domains where you don't want the output valid to de-assert.

val hierarchical_with_delay : ?name:string -> ?delay:int -> Scope.t -> Signal.t I.t -> Signal.t O.t
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