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package hardcaml
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Module Cyclesim.PrivateSource

Sourcetype port_list = Port_list.t
Sourcetype node = Node.t
Sourcetype reg = Reg.t
Sourcetype memory = Memory.t
Sourcetype task = Base.unit -> Base.unit
Sourceval create : ?circuit:Circuit.t -> in_ports:port_list -> out_ports_before_clock_edge:port_list -> out_ports_after_clock_edge:port_list -> reset:task -> cycle_check:task -> cycle_before_clock_edge:task -> cycle_at_clock_edge:task -> cycle_after_clock_edge:task -> traced:Traced.t -> lookup_node:(Traced.internal_signal -> node Base.option) -> lookup_reg:(Traced.internal_signal -> reg Base.option) -> lookup_mem:(Traced.internal_signal -> memory Base.option) -> Base.unit -> t_port_list
Sourcemodule Step : sig ... end
Sourceval modify : ('i, 'o) t -> (Side.t * Step.t * task) Base.list -> ('i, 'o) t
Sourceval coerce : (port_list, port_list) t -> to_input:(port_list -> 'i) -> to_output:(port_list -> 'o) -> ('i, 'o) t
Sourcemodule Traced_nodes : sig ... end
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