package hardcaml

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package hardcaml
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Utility functions for clock domain crossings.

val stretch : Signal.t t -> n:int -> Signal.t -> Signal.t

Take a single cycle input pulse, and stretch it for n cycles. The output goes high on the same cycle as the input.

val stretch_no_clear : Signal.t t -> n:int -> Signal.t -> Signal.t
val with_valid_pulse_detect_rising_edge : Signal.t t -> Signal.t With_valid.t -> Signal.t With_valid.t

Take a Signal.t With_valid.t that is in a slower clock and convert the valid pulse to a pulse in the faster clock.

val reg_no_clear_with_async_reg_annotation : num_additional_pipeline_stages:int -> Signal.t t -> Signal.t -> Signal.t

Create 1 + num_additional_pipeline_stages registers in a pipeline with async_reg attribute set

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