package hardcaml

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package hardcaml
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Module Rtl.NameSource

Sourcemodule type Language = sig ... end
Sourcetype t
Sourceval create : (module Language) -> t
Sourceval legalize : t -> Base.string -> Base.string
Sourceval add_port_name : t -> Signal.t -> Base.string -> Base.unit
Sourceval add_phantom_port_name : t -> Base.string -> Base.unit
Sourceval mangle_name : t -> Base.string -> Base.string
Sourceval mangle_signal_names : t -> Signal.t -> Base.string Base.list
Sourceval mangle_instantiation_name : t -> Signal.t -> Base.string
Sourceval mangle_multiport_mem_name : t -> Signal.t -> Base.string * Base.string

Returns the mangled name for the memory array, and (in VHDL) array type.