package hardcaml

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package hardcaml
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Library
Module
Module type
Parameter
Class
Class type
module type Language = sig ... end
module Verilog : Language
module Vhdl : Language
type t
val create : (module Language) -> t
val legalize : t -> Base.string -> Base.string
val add_port_name : t -> Signal.t -> Base.string -> Base.unit
val add_phantom_port_name : t -> Base.string -> Base.unit
val mangle_name : t -> Base.string -> Base.string
val mangle_signal_names : t -> Signal.t -> Base.string Base.list
val mangle_instantiation_name : t -> Signal.t -> Base.string
val mangle_multiport_mem_name : t -> Signal.t -> Base.string * Base.string

Returns the mangled name for the memory array, and (in VHDL) array type.

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