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package hardcaml
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Module Cyclesim.MemorySource

Read and write access for memories. They have much the same API as Nodes. and Regs except for an extra address argument.

Sourcetype t
Sourceval width_in_bits : t -> Base.int
Sourceval size_in_words : t -> Base.int
Sourceval memory_size : t -> Base.int
Sourceval create_from_bits_mutable_array : Bits.Mutable.t Base.array -> t
Sourceval create_from_read_only_bits_array : Bits.t Base.array -> t
Sourceval create_from_signal : byte_address:Base.int -> data:Base.Bytes.t -> Signal.t -> t
Sourceval unsafe_set64 : t -> address:Base.int -> Base.int -> Base.Int64.t -> Base.unit
Sourceval unsafe_get64 : t -> address:Base.int -> Base.int -> Base.Int64.t
Sourceval set64 : t -> address:Base.int -> Base.int -> Base.Int64.t -> Base.unit
Sourceval get64 : t -> address:Base.int -> Base.int -> Base.Int64.t
Sourceval of_bits_mutable : t -> address:Base.int -> Bits.Mutable.t -> Base.unit
Sourceval to_bits_mutable : t -> address:Base.int -> Bits.Mutable.t -> Base.unit
Sourceval of_bits : t -> address:Base.int -> Bits.t -> Base.unit
Sourceval to_bits : t -> address:Base.int -> Bits.t
Sourceval to_int : t -> address:Base.int -> Base.int
Sourceval of_int : t -> address:Base.int -> Base.int -> Base.unit
Sourceval read_all : t -> Bits.t Base.array
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