package hardcaml

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package hardcaml
Legend:
Library
Module
Module type
Parameter
Class
Class type

RTL generation options.

RTL generation options.

type t =
  1. | In_directory of Base.string
    (*

    Write each circuit into a file in the given directory. The file name consists of the circuit name and the approriate file extension (.v for Verilog and .vhd for VHDL).

    *)
  2. | To_buffer of Base.Buffer.t
    (*

    Write all circuits into one buffer.

    *)
  3. | To_channel of Stdio.Out_channel.t
    (*

    Write all circuits to one out channel.

    *)
  4. | To_file of Base.string
    (*

    Write all circuits into one file.

    *)
val sexp_of_t : t -> Sexplib0.Sexp.t
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