package hardcaml_of_verilog

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package hardcaml_of_verilog
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Helper functions to ease usage of the Always API when working with interfaces.

Assign a interface containing variables in an always block.

Creates a interface container with register variables.

Creates a interface container with wire variables, e.g. Foo.Of_always.wire Signal.zero, which would yield wires defaulting to zero.

val apply_names : ?prefix:Base.string -> ?suffix:Base.string -> ?naming_op:(Hardcaml.Signal.t -> Base.string -> Hardcaml.Signal.t) -> Hardcaml.Always.Variable.t t -> Base.unit

Apply names to field of the interface. Add prefix and suffix if specified.