package hardcaml_of_verilog

You can search for identifiers within the package.

in-package search v0.2.0

hardcaml_of_verilog
- Hardcaml_of_verilog
  - Circuit_to_json
  - Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    V
    
    Bit
    
    Cell
    
    V
    
    Connection
    
    V
    
    Direction
    
    Int_or_string
    
    Module
    
    V
    
    Netname
    
    V
    
    Parameter
    
    V
    
    Port
    
    V
    
    Port_direction
    
    V
  - Netlist
    
    Bit
    
    Bus
    
    Bus_names
    
    Cell
    
    Module
    
    Parameter
    
    Port
  - Ocaml_module
    
    Rebuild_interfaces
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    X
  - Pass
  - Verilog_circuit
  - Verilog_design
    
    Crunched
    
    Define
    
    Define_value
    
    Defines
    
    Embedded_files
    
    Module
    
    Parameter
    
    Parameters
  - With_interface
    
    Make
    
    I
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
    
    O
    
    All
    
    M
    
    Let_syntax
    
    Let_syntax
    
    Open_on_rhs
    
    Monad_infix
    
    Comb
    
    Make_comb
    
    Comb
    
    Signed
    
    Sop
    
    Typed_math
    
    Unsigned
    
    Uop
    
    Names_and_widths
    
    Of_always
    
    Of_bits
    
    Of_signal
    
    Unsafe_assoc_by_port_name
hardcaml_of_verilog.port
- Hardcaml_port_verilog
  - Make
    
    X

Legend:
Library
Module
Module type
Parameter
Class
Class type

module Parameter : sig ... end

module Parameters : sig ... end

module Define_value : sig ... end

module Define : sig ... end

module Defines : sig ... end

module Module : sig ... end

type t

include Sexplib0.Sexpable.S with type t := t

val t_of_sexp : Sexplib0.Sexp.t -> t

val sexp_of_t : t -> Sexplib0.Sexp.t

val create : ?defines:Defines.t -> top:Module.t -> Base.unit -> t

val defines : t -> Defines.t

val top : t -> Module.t

val top_name : t -> Base.string

Name of top level module

val override_parameters : t -> Parameters.t -> t

Override the parameters of the top level module

val map_paths : t -> f:(Base.string -> Base.string) -> t

map_paths t ~f applies f to each modules path

module type Crunched = sig ... end

val map_crunched_paths : 
  ?delete_temp_files:Base.bool ->
  (module Crunched) Base.list ->
  t ->
  t

Read verilog files from ocaml-cruched file system(s) and extract to temp files.

module type Embedded_files = sig ... end

val map_embed_file_paths : 
  ?delete_temp_files:Base.bool ->
  (module Embedded_files) Base.list ->
  t ->
  t

Read verilog files from embed_file file system(s) and extract to temp files.