package hardcaml_of_verilog

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package hardcaml_of_verilog
Legend:
Library
Module
Module type
Parameter
Class
Class type
module Circuit_to_json : sig ... end

Takes in a Hardcaml circuit and transforms it to a json file that can be read and rendered by netlistsvg.

module Netlist : sig ... end

Netlist representing a verilog design synthesized with yosys.

module Ocaml_module : sig ... end

Static construction of an ocaml module with hardcaml interfaces that dynamically loads the implementation at runtime. Interface widths are adjusted based on instantiation parameters.

module Pass : sig ... end
module Verilog_circuit : sig ... end

A data structure representing the hardcaml implementation of a Verilog_design.t converted to a Netlist.t.

module Verilog_design : sig ... end
module With_interface : sig ... end
module Expert : sig ... end