package hardcaml_of_verilog

  1. Overview
  2. Docs
Convert Verilog to a Hardcaml design

Install

github.com Readme Changelog MIT License Edit opam file

Authors

  1. J
    Jane Street Group, LLC

Maintainers

  1. J
    Jane Street developers

Sources

hardcaml_of_verilog-v0.16.0.tar.gz
sha256=d0c73140e80b48f7e971d6fa94e7f8ed8aa64cd7685d0fb442eb590ba6a244b4

Description

The opensource synthesis tool yosys is used to convert a verilog design to a JSON based netlist representation. This library can load the JSON netlist and build a hardcaml circuit.

Code can also be generated to wrap the conversion process using Hardcaml interfaces.

Published: 14 Jun 2023

Dependencies (12)

  1. dune >= "2.0.0"
  2. stdio >= "v0.16" & < "v0.17"
  3. ppx_jsonaf_conv >= "v0.16" & < "v0.17"
  4. ppx_jane >= "v0.16" & < "v0.17"
  5. ppx_deriving_hardcaml >= "v0.16" & < "v0.17"
  6. jsonaf >= "v0.16" & < "v0.17"
  7. hardcaml_verify >= "v0.16" & < "v0.17"
  8. hardcaml >= "v0.16" & < "v0.17"
  9. core_unix >= "v0.16" & < "v0.17"
  10. core >= "v0.16" & < "v0.17"
  11. base >= "v0.16" & < "v0.17"
  12. ocaml >= "4.14.0"

Dev Dependencies

None

Used by

None

Conflicts

None