package hardcaml_of_verilog

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Convert Verilog to a Hardcaml design

Install 

dune-project
 Dependency

github.com Edit opam file Versions (3)

Authors

  1. J
    Jane Street Group, LLC

Maintainers

  1. J
    Jane Street developers

Sources

v0.17.0.tar.gz
sha256=8603da93ce48dc3e550043310ab3b5c0da3bc19f04391ade7bcc8c46dc3e612d

Description

The opensource synthesis tool yosys is used to convert a verilog design to a JSON based netlist representation. This library can load the JSON netlist and build a hardcaml circuit.

Code can also be generated to wrap the conversion process using Hardcaml interfaces.

Published: 26 May 2024

Dependencies (12)

  1. dune >= "3.11.0"
  2. stdio >= "v0.17" & < "v0.18~"
  3. ppx_jsonaf_conv >= "v0.17" & < "v0.18~"
  4. ppx_jane >= "v0.17" & < "v0.18~"
  5. ppx_hardcaml >= "v0.17" & < "v0.18~"
  6. jsonaf >= "v0.17" & < "v0.18~"
  7. hardcaml_verify >= "v0.17" & < "v0.18~"
  8. hardcaml >= "v0.17" & < "v0.18~"
  9. core_unix >= "v0.17" & < "v0.18~"
  10. core >= "v0.17" & < "v0.18~"
  11. base >= "v0.17" & < "v0.18~"
  12. ocaml >= "5.1.0"

Dev Dependencies

None

Used by

None

Conflicts

None