package hardcaml_of_verilog
Convert Verilog to a Hardcaml design
Install
Authors
Maintainers
Sources
hardcaml_of_verilog-v0.16.0.tar.gz
sha256=d0c73140e80b48f7e971d6fa94e7f8ed8aa64cd7685d0fb442eb590ba6a244b4
Description
The opensource synthesis tool yosys is used to convert a verilog design to a JSON based netlist representation. This library can load the JSON netlist and build a hardcaml circuit.
Code can also be generated to wrap the conversion process using Hardcaml interfaces.
Published: 14 Jun 2023
Dependencies (12)
-
dune
>= "2.0.0"
-
stdio
>= "v0.16" & < "v0.17"
-
ppx_jsonaf_conv
>= "v0.16" & < "v0.17"
-
ppx_jane
>= "v0.16" & < "v0.17"
-
ppx_deriving_hardcaml
>= "v0.16" & < "v0.17"
-
jsonaf
>= "v0.16" & < "v0.17"
-
hardcaml_verify
>= "v0.16" & < "v0.17"
-
hardcaml
>= "v0.16" & < "v0.17"
-
core_unix
>= "v0.16" & < "v0.17"
-
core
>= "v0.16" & < "v0.17"
-
base
>= "v0.16" & < "v0.17"
-
ocaml
>= "4.14.0"
Dev Dependencies
Used by
Conflicts
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