package hardcaml_of_verilog

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Module Netlist.PortSource

Sourcetype 'a t = {
  1. name : Base.string;
  2. value : 'a;
}
Sourceval sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
Sourceval value : 'a t -> 'a
Sourceval name : 'a t -> Base.string
Sourceval find_exn : 'a t Base.list -> Base.string -> 'a t
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