package hardcaml_of_verilog

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Signature

hardcaml_of_verilog
- CHANGES
- LICENSE
- README
- Library hardcaml_of_verilog
  - Hardcaml_of_verilog
    
    Circuit_to_json
    
    Netlist
    
    Bit
    
    Bus
    
    Parameter
    
    Port
    
    Cell
    
    Bus_names
    
    Module
    
    Ocaml_module
    
    Rebuild_interfaces
    
    I
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    O
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Pass
    
    Verilog_circuit
    
    Port
    
    Verilog_design
    
    Parameter
    
    Parameters
    
    Define_value
    
    Define
    
    Defines
    
    Module
    
    Crunched
    
    Embedded_files
    
    With_interface
    
    Make
    
    Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    Assoc_list
    
    Int_or_string
    
    Direction
    
    Bit
    
    Port
    
    V
    
    Parameter
    
    V
    
    Connection
    
    V
    
    Port_direction
    
    V
    
    Cell
    
    V
    
    Netname
    
    V
    
    Module
    
    V
- Library hardcaml_of_verilog.port
  - Hardcaml_port_verilog
    
    Make
- Sources
  - hardcaml_of_verilog
    
    circuit_bus_map.ml
    
    circuit_to_json.ml
    
    config.ml
    
    hardcaml_of_verilog.ml
    
    hardcaml_of_verilog__.ml
    
    lvt.ml
    
    netlist.ml
    
    ocaml_module.ml
    
    pass.ml
    
    synthesize.ml
    
    techlib.ml
    
    verilog_circuit.ml
    
    verilog_design.ml
    
    with_interface.ml
    
    yosys_netlist.ml
  - hardcaml_of_verilog.port
    
    hardcaml_port_verilog.ml
    
    hardcaml_port_verilog__.ml
    
    port_verilog.ml

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Source

Module `With_interface.Make`Source

Parameters

module I : Hardcaml.Interface.S

module O : Hardcaml.Interface.S

Signature

Source

val create : 
  ?verbose:Base.bool ->
  ?passes:Pass.t Base.list ->
  Verilog_design.t ->
  (Hardcaml.Signal.t I.t ->
    Hardcaml.Signal.t O.t Base.Or_error.t)
    Base.Or_error.t

package hardcaml_of_verilog

Module With_interface.MakeSource

Parameters

Signature

Module `With_interface.Make`Source