package hardcaml_of_verilog

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package hardcaml_of_verilog
Legend:
Library
Module
Module type
Parameter
Class
Class type

Netlist representing a verilog design synthesized with yosys.

The conversion is done lazily when a module is referenced.

module Bit : sig ... end
module Bus : sig ... end
module Parameter : sig ... end
module Port : sig ... end
module Cell : sig ... end
module Bus_names : sig ... end
module Module : sig ... end
type t
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : ?verbose:Base.bool -> ?passes:Pass.t Base.list -> Verilog_design.t -> t Base.Or_error.t

Synthesize a Verilog_design into a netlist.

val find_module_by_name : t -> Base.string -> Module.t Base.Or_error.t

Get a module from the netlist by module name. Note that conversion actally happens on lookup, hence the error return (this allows us to selectively convert modules from a netlist, without needing all of them to be correct).

val get_all_modules : t -> Module.t Base.list Base.Or_error.t

Return all modules in the netlist

val of_yosys_netlist : Hardcaml_of_verilog__.Yosys_netlist.t -> t Base.Or_error.t

Convert a raw yosys netlist.