package hardcaml_of_verilog

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hardcaml_of_verilog
- CHANGES
- LICENSE
- README
- Library hardcaml_of_verilog
  - Hardcaml_of_verilog
    
    Circuit_to_json
    
    Netlist
    
    Bit
    
    Bus
    
    Parameter
    
    Port
    
    Cell
    
    Bus_names
    
    Module
    
    Ocaml_module
    
    Rebuild_interfaces
    
    I
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    O
    
    Unsafe_assoc_by_port_name
    
    All
    
    Comb
    
    Make_comb
    
    Of_bits
    
    Of_signal
    
    Of_always
    
    Names_and_widths
    
    Pass
    
    Verilog_circuit
    
    Port
    
    Verilog_design
    
    Parameter
    
    Parameters
    
    Define_value
    
    Define
    
    Defines
    
    Module
    
    Crunched
    
    Embedded_files
    
    With_interface
    
    Make
    
    Expert
    
    Synthesize
    
    Yosys_netlist
    
    Assoc_list
    
    Assoc_list
    
    Int_or_string
    
    Direction
    
    Bit
    
    Port
    
    V
    
    Parameter
    
    V
    
    Connection
    
    V
    
    Port_direction
    
    V
    
    Cell
    
    V
    
    Netname
    
    V
    
    Module
    
    V
- Library hardcaml_of_verilog.port
  - Hardcaml_port_verilog
    
    Make
- Sources
  - hardcaml_of_verilog
    
    circuit_bus_map.ml
    
    circuit_to_json.ml
    
    config.ml
    
    hardcaml_of_verilog.ml
    
    hardcaml_of_verilog__.ml
    
    lvt.ml
    
    netlist.ml
    
    ocaml_module.ml
    
    pass.ml
    
    synthesize.ml
    
    techlib.ml
    
    verilog_circuit.ml
    
    verilog_design.ml
    
    with_interface.ml
    
    yosys_netlist.ml
  - hardcaml_of_verilog.port
    
    hardcaml_port_verilog.ml
    
    hardcaml_port_verilog__.ml
    
    port_verilog.ml

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Module `Hardcaml_of_verilog.Netlist`Source

Netlist representing a verilog design synthesized with yosys.

The conversion is done lazily when a module is referenced.

Sourcemodule Bit : sig ... end

Sourcemodule Bus : sig ... end

Sourcemodule Parameter : sig ... end

Sourcemodule Port : sig ... end

Sourcemodule Cell : sig ... end

Sourcemodule Bus_names : sig ... end

Sourcemodule Module : sig ... end

Sourcetype t

Sourceval sexp_of_t : t -> Sexplib0.Sexp.t

Source

val create : 
  ?verbose:Base.bool ->
  ?passes:Pass.t Base.list ->
  Verilog_design.t ->
  t Base.Or_error.t

Synthesize a Verilog_design into a netlist.

Sourceval find_module_by_name : t -> Base.string -> Module.t Base.Or_error.t

Get a module from the netlist by module name. Note that conversion actally happens on lookup, hence the error return (this allows us to selectively convert modules from a netlist, without needing all of them to be correct).

Sourceval get_all_modules : t -> Module.t Base.list Base.Or_error.t

Return all modules in the netlist

Source

val of_yosys_netlist : 
  Hardcaml_of_verilog__.Yosys_netlist.t ->
  t Base.Or_error.t

Convert a raw yosys netlist.

package hardcaml_of_verilog

Module Hardcaml_of_verilog.NetlistSource

Module `Hardcaml_of_verilog.Netlist`Source