package hardcaml_of_verilog

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package hardcaml_of_verilog
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Module Netlist.BitSource

Sourcetype t =
  1. | Vdd
  2. | Gnd
  3. | X
  4. | Index of Base.int
include Ppx_compare_lib.Comparable.S with type t := t
Sourceval compare : t -> t -> int
include Ppx_jsonaf_conv_lib.Jsonafable.S with type t := t
Sourceval t_of_jsonaf : Jsonaf_kernel__.Type.t -> t
Sourceval jsonaf_of_t : t -> Jsonaf_kernel__.Type.t
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
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