package hardcaml_of_verilog

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type t =
  1. | Input
  2. | Output
include Ppx_compare_lib.Equal.S with type t := t
val equal : t -> t -> bool
include Ppx_jsonaf_conv_lib.Jsonafable.S with type t := t
val t_of_jsonaf : Jsonaf_kernel__.Type.t -> t
val jsonaf_of_t : t -> Jsonaf_kernel__.Type.t
val sexp_of_t : t -> Sexplib0.Sexp.t