package hardcaml_of_verilog

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package hardcaml_of_verilog
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Module
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Class
Class type
val yosys_script : ?passes:Pass.t Base.list -> Verilog_design.t -> json_file:Base.string -> Base.string
val to_json_file : ?verbose:Base.bool -> ?passes:Pass.t Base.list -> Verilog_design.t -> json_file:Base.string -> Base.unit Base.Or_error.t
val to_yosys_netlist : ?verbose:Base.bool -> ?passes:Pass.t Base.list -> Verilog_design.t -> Hardcaml_of_verilog__.Yosys_netlist.t Base.Or_error.t