package hardcaml_of_verilog

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package hardcaml_of_verilog
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val iter : 'a t -> name: (('a t, Base.string) Fieldslib.Field.t -> 'a t -> Base.string -> Base.unit) -> value:(('a t, 'a) Fieldslib.Field.t -> 'a t -> 'a -> Base.unit) -> Base.unit
val fold : 'a t -> init:'acc__0 -> name: ('acc__0 -> ('a t, Base.string) Fieldslib.Field.t -> 'a t -> Base.string -> 'acc__1) -> value:('acc__1 -> ('a t, 'a) Fieldslib.Field.t -> 'a t -> 'a -> 'acc__2) -> 'acc__2
val for_all : 'a t -> name: (('a t, Base.string) Fieldslib.Field.t -> 'a t -> Base.string -> Base.bool) -> value:(('a t, 'a) Fieldslib.Field.t -> 'a t -> 'a -> Base.bool) -> Base.bool
val exists : 'a t -> name: (('a t, Base.string) Fieldslib.Field.t -> 'a t -> Base.string -> Base.bool) -> value:(('a t, 'a) Fieldslib.Field.t -> 'a t -> 'a -> Base.bool) -> Base.bool
val to_list : 'a t -> name: (('a t, Base.string) Fieldslib.Field.t -> 'a t -> Base.string -> 'elem__) -> value:(('a t, 'a) Fieldslib.Field.t -> 'a t -> 'a -> 'elem__) -> 'elem__ Base.list
val map : 'a t -> name: (('a t, Base.string) Fieldslib.Field.t -> 'a t -> Base.string -> Base.string) -> value:(('a t, 'a) Fieldslib.Field.t -> 'a t -> 'a -> 'a) -> 'a t
val set_all_mutable_fields : 'a t -> Base.unit