package hardcaml_of_verilog

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package hardcaml_of_verilog
Legend:
Library
Module
Module type
Parameter
Class
Class type
type t = {
  1. name : Base.string;
  2. inputs : Bus.t Port.t Base.list;
  3. outputs : Bus.t Port.t Base.list;
  4. cells : Cell.t Base.list;
  5. bus_names : Bus_names.t;
}
val sexp_of_t : t -> Sexplib0.Sexp.t
val sanitize_instance_names : t -> t