package hardcaml_of_verilog

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package hardcaml_of_verilog
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A data structure representing the hardcaml implementation of a Verilog_design.t converted to a Netlist.t.

module Port = Netlist.Port
type t
val sexp_of_t : t -> Sexplib0.Sexp.t
val create : Netlist.t -> top_name:Base.string -> t Base.Or_error.t
val inputs : t -> Base.int Port.t Base.list
val outputs : t -> Base.int Port.t Base.list
val to_hardcaml_circuit : t -> Hardcaml.Circuit.t Base.Or_error.t