package hardcaml_of_verilog

  1. Overview
  2. Docs

Parameters

module X : sig ... end

Signature

val verilog_design : Verilog_design.t
module I : Hardcaml.Interface.S with type 'a t = 'a I.t
module O : Hardcaml.Interface.S with type 'a t = 'a O.t