package hardcaml_of_verilog

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package hardcaml_of_verilog
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Module
Module type
Parameter
Class
Class type
val value : ('a t, 'a) Fieldslib.Field.t
val fold : init:'acc__0 -> name:('acc__0 -> ('a t, Base.string) Fieldslib.Field.t -> 'acc__1) -> value:('acc__1 -> ('a t, 'a) Fieldslib.Field.t -> 'acc__2) -> 'acc__2
val make_creator : name: (('a t, Base.string) Fieldslib.Field.t -> 'acc__0 -> ('input__ -> Base.string) * 'acc__1) -> value:(('a t, 'a) Fieldslib.Field.t -> 'acc__1 -> ('input__ -> 'a) * 'acc__2) -> 'acc__0 -> ('input__ -> 'a t) * 'acc__2
val create : name:Base.string -> value:'a -> 'a t
val map : name:(('a t, Base.string) Fieldslib.Field.t -> Base.string) -> value:(('a t, 'a) Fieldslib.Field.t -> 'a) -> 'a t
val iter : name:(('a t, Base.string) Fieldslib.Field.t -> Base.unit) -> value:(('a t, 'a) Fieldslib.Field.t -> Base.unit) -> Base.unit
val for_all : name:(('a t, Base.string) Fieldslib.Field.t -> Base.bool) -> value:(('a t, 'a) Fieldslib.Field.t -> Base.bool) -> Base.bool
val exists : name:(('a t, Base.string) Fieldslib.Field.t -> Base.bool) -> value:(('a t, 'a) Fieldslib.Field.t -> Base.bool) -> Base.bool
val to_list : name:(('a t, Base.string) Fieldslib.Field.t -> 'elem__) -> value:(('a t, 'a) Fieldslib.Field.t -> 'elem__) -> 'elem__ Base.list
val map_poly : ([< `Read | `Set_and_create ], 'a t, 'x0) Fieldslib.Field.user -> 'x0 Base.list
module Direct : sig ... end