package hardcaml_of_verilog

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type t = {
  1. hide_name : Base.int;
  2. module_name : Base.string;
  3. parameters : Parameter.t Base.list;
  4. port_directions : Port_direction.t Base.list;
  5. connections : Connection.t Base.list;
}
include Ppx_jsonaf_conv_lib.Jsonafable.S with type t := t
val t_of_jsonaf : Jsonaf_kernel__.Type.t -> t
val jsonaf_of_t : t -> Jsonaf_kernel__.Type.t
val sexp_of_t : t -> Sexplib0.Sexp.t