package hardcaml

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type 'a same = 'a Base.List.t
val smap : f:(var -> Signal.t) -> var same -> Signal.t same
val new_var : Base.Unit.t -> var same t
val read : var same -> Signal.t same t
val rewrite : (Signal.t same -> Signal.t same) -> var same -> var same -> Base.Unit.t t
val apply : f:(Signal.t same -> Signal.t same) -> var same -> Base.Unit.t t
val set : var same -> Signal.t same -> Base.Unit.t t
val if_ : (Signal.t same -> Signal.t) -> var same -> then_:'a t -> else_:'b t -> Base.Unit.t t
val while_ : (Signal.t same -> Signal.t) -> var same -> do_:'a t -> 'a t
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