Creation and manipulation of hardware circuits
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.ttype 'a with_create_options =
?detect_combinational_loops:Hardcaml__.Import.Bool.t ->
?normalize_uids:Hardcaml__.Import.Bool.t ->
'awith_create_options specifies the optional arguments that can be supplied to create_exn.
detect_combinational_loops determines whether create_exn ensures that there is no path from a signal to itself that does not pass through a register or memory.
normalize_uids determines whether create_exn renumbers the uids of all signals in the circuit starting at one. Uid normalization ensures that circuits will print the same (as sexps or rtl) regardless of the environment in which they are constructed (in particular with regard to the global uid generator).
val create_exn :
(name:Hardcaml__.Import.String.t ->
Signal.t Hardcaml__.Import.List.t ->
t)
with_create_optionscreate circuit data structure
val signal_graph : t -> Signal_graph.tval name : t -> Hardcaml__.Import.String.treturn circuit name
Return identical circuit except for the name.
val find_signal_exn : t -> Signal.Uid.t -> Signal.tval set_phantom_inputs :
t ->
(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t ->
tFor internal use. Add phantom input ports to the circuit when writing RTL. This can be necessary to ensure Interface based input specifications match those discovered when traversing the hardware design from its outputs. It is especially important when working with hierarchical designs.
val phantom_inputs :
t ->
(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.tmodule Signal_map : sig ... endMap of uids to Signal.ts.
val signal_map : t -> Signal_map.tGet map of uids to Signal.ts.
val fan_out_map : t -> Signal.Uid_set.t Signal.Uid_map.tCompute and return a Fan_out_map.t. The computation is lazy and only performed the first time fan_out_map is called.
val fan_in_map : t -> Signal.Uid_set.t Signal.Uid_map.tCompute and return a Fan_in_map.t. The computation is lazy and only performed the first time fan_in_map is called.
val structural_compare :
?check_names:Hardcaml__.Import.Bool.t ->
t ->
t ->
Hardcaml__.Import.Bool.tcompare 2 circuits to see if they are the same
module Create_options : sig ... endCreate_options is a record with one field for each with_create_options argument. It allows one to define a function of type _ with_create_options that takes the same optional arguments as create_exn and to pass those options on to create_exn, without every having to directly refer to any of the arguments. This makes wrapper code robust to changes in what the optional arguments are. Here is the usage idiom:
val with_create_options : (Create_options.t -> 'a) -> 'a with_create_optionsval call_with_create_options : 'a with_create_options -> Create_options.t -> 'amodule Port_checks : sig ... endCheck if the ports specified in the interface match those defined in the circuit.
module With_interface (I : Interface.S) (O : Interface.S) : sig ... end