package hardcaml

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package hardcaml
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Library
Module
Module type
Parameter
Class
Class type

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

In Verilog they are called parameterss and in VHDL they are called generics.

module Std_logic : sig ... end

9-state VHDL std_logic enumeration

module Std_logic_vector : sig ... end
module Bit_vector : sig ... end
module Value : sig ... end
type t = {
  1. name : Parameter_name.t;
  2. value : Value.t;
}
val compare : t -> t -> Base.Int.t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val equal : t Base__Equal.equal
module Unstable : sig ... end
val create : name:Hardcaml__.Import.String.t -> value:Value.t -> t
val find_name : t Hardcaml__.Import.List.t -> Parameter_name.t -> Value.t Hardcaml__.Import.Option.t
val find_name_exn : t Hardcaml__.Import.List.t -> Parameter_name.t -> Value.t
val is_subset : t Hardcaml__.Import.List.t -> t Hardcaml__.Import.List.t -> Hardcaml__.Import.Bool.t

is_subset ts1 ts2 returns true iff every t in ts1 is in ts2.

val sort_by_name : t Hardcaml__.Import.List.t -> t Hardcaml__.Import.List.t
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