Icarus Verilog Cosimulation interface (DEPRECATED)
run sets, then gets then schedule next callback at cur_time+delta_time
control message
module Comms : sig ... endbasic TCP communications between client (simulation) and server (hardcaml)
val control : Unix.file_descr -> control_message -> response_messagesend a control message to the simulation
val write_testbench :
?dump_file:string ->
name:string ->
inputs:(string * int) list ->
outputs:(string * int) list ->
(string -> unit) ->
unitwrite test harness
val write_testbench_from_circuit :
?dump_file:string ->
(string -> unit) ->
Circuit.t ->
unitwrite test hardness derivied from a hardcaml circuit
val derive_clocks_and_resets : Circuit.t -> string list * string listfind clocks and resets in a hardcaml circuit
module type Simulator = sig ... end