package hardcaml

  1. Overview
  2. Docs
package hardcaml
Legend:
Library
Module
Module type
Parameter
Class
Class type

Icarus Verilog Cosimulation interface (DEPRECATED)

type delta_message = {
  1. sets : (Hardcaml__.Import.String.t * Hardcaml__.Import.String.t) Hardcaml__.Import.List.t;
  2. gets : Hardcaml__.Import.String.t Hardcaml__.Import.List.t;
  3. delta_time : Base.Int64.t;
}

run sets, then gets then schedule next callback at cur_time+delta_time

type init_message = Hardcaml__.Import.String.t Hardcaml__.Import.List.t

expected inputs and outputs

type control_message =
  1. | Finish
  2. | Run of delta_message

control message

type response_message = (Hardcaml__.Import.String.t * Hardcaml__.Import.String.t) Hardcaml__.Import.List.t

response message

val net_addr : Hardcaml__.Import.String.t
val net_port : Base.Int.t
module Comms : sig ... end

basic TCP communications between client (simulation) and server (hardcaml)

val control : Unix.file_descr -> control_message -> response_message

send a control message to the simulation

val write_testbench : ?dump_file:Hardcaml__.Import.String.t -> name:Hardcaml__.Import.String.t -> inputs:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> outputs:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> (Hardcaml__.Import.String.t -> Hardcaml__.Import.Unit.t) -> Hardcaml__.Import.Unit.t

write test harness

val write_testbench_from_circuit : ?dump_file:Hardcaml__.Import.String.t -> (Hardcaml__.Import.String.t -> Hardcaml__.Import.Unit.t) -> Circuit.t -> Hardcaml__.Import.Unit.t

write test hardness derivied from a hardcaml circuit

val compile : Hardcaml__.Import.String.t Hardcaml__.Import.List.t -> Hardcaml__.Import.String.t -> Hardcaml__.Import.Unit.t

compile verilog files to a vvp simulation object

val derive_clocks_and_resets : Circuit.t -> Hardcaml__.Import.String.t Hardcaml__.Import.List.t * Hardcaml__.Import.String.t Hardcaml__.Import.List.t

find clocks and resets in a hardcaml circuit

val load_sim : Hardcaml__.Import.String.t -> Hardcaml__.Import.Unit.t

load vvp file into simulator along with vpi object

val compile_and_load_sim : ?dump_file:Hardcaml__.Import.String.t -> Circuit.t -> Hardcaml__.Import.Unit.t

compile circuit and load simulation

val init_sim : (Hardcaml__.Import.Unit.t -> Hardcaml__.Import.Unit.t) -> (Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> (Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> Unix.file_descr
val make_sim_obj : server:Unix.file_descr -> clocks:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> resets:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> inputs:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> outputs:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> Cyclesim.t_port_list
val make : ?dump_file:Hardcaml__.Import.String.t -> Circuit.t -> Cyclesim.t_port_list

create simulator from hardcaml circuit

val load : clocks:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> resets:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> inputs:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> outputs:(Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t -> Hardcaml__.Import.String.t -> Cyclesim.t_port_list

load icarus vvp simulation

module With_interface (I : Interface.S) (O : Interface.S) : sig ... end
OCaml

Innovation. Community. Security.

GitHub Discord Twitter Peertube RSS
About
Changelog Releases Industrial Users Academic Users Why OCaml
Ecosystem
Packages Community Events OCaml Planet Jobs
Resources
Install OCaml Get Started Platform Tools Language Manual Standard Library API Books Exercises Papers OCaml Playground Logo
Policies
Carbon Footprint Governance Privacy Code of Conduct