Support for hierarchically structured Hardcaml designs. We extend the standard Interface.Create_fn pattern so that the creation function also takes a Scope.t argument. This allows scoping of signal naming and automatic recording of the design in a Circuit_database.t. Top level options allow construction of a flat or modular design as required for simulation or syntheis.
module I : Interface.Smodule O : Interface.Stype create = Scope.t -> Signal.t Interface.Create_fn(I)(O).tval create :
scope:Scope.t ->
name:Hardcaml__.Import.String.t ->
create ->
Circuit.With_interface(I)(O).createCreate a Hardcaml child design and link it into the parent design. This will not form a hierarchical structure, but the signal naming will still be scoped.
val hierarchical :
(?port_checks:Circuit.Port_checks.t ->
?add_phantom_inputs:Hardcaml__.Import.Bool.t ->
?instance:Hardcaml__.Import.String.t ->
scope:Scope.t ->
name:Hardcaml__.Import.String.t ->
create ->
Circuit.With_interface(I)(O).create)
Circuit.with_create_optionsCreate a Hardcaml child design hierarchically, depending on the construction mode. In a flat design In_scope.create is called. In a hierarchical design a circuit is constructed, added to a Circuit_database.t and an instantiation inserted into the parent design.
The instance parameter can be used to specify the instantiation and scope name, if provided. Otherwise name is used as the scope name, and the instantiation name is derived automatically.