Write circuit as graph.
val write_dot_rank :
Hardcaml__.Import.Out_channel.t ->
Circuit.t ->
Hardcaml__.Import.Unit.tval write_gdl :
?names:Hardcaml__.Import.Bool.t ->
?widths:Hardcaml__.Import.Bool.t ->
?consts:Hardcaml__.Import.Bool.t ->
?clocks:Hardcaml__.Import.Bool.t ->
Hardcaml__.Import.Out_channel.t ->
Circuit.t ->
Hardcaml__.Import.Unit.twrite a GDL (graph description language) file of the given circuit
val aisee3 :
?args:Hardcaml__.Import.String.t ->
?names:Hardcaml__.Import.Bool.t ->
?widths:Hardcaml__.Import.Bool.t ->
?consts:Hardcaml__.Import.Bool.t ->
?clocks:Hardcaml__.Import.Bool.t ->
Circuit.t ->
Hardcaml__.Import.Unit.tlaunch aisee3 to visualize the given circuit