package hardcaml
Module Always.State_machineSource
Source
type 'a t = {current : Signal.t;is : 'a -> Signal.t;set_next : 'a -> always;(*
*)switch casesdoes a switch on all possible states. The cases must be exhaustive and irredundant. If the cases are non-exhaustive, one can supply~defaultto make them exhaustive.switch : ?default:always Base.List.t -> 'a cases -> always;
}Source
val create :
?encoding:Encoding.t ->
(module State with type t = 'a) ->
Reg_spec.t ->
enable:Signal.t ->
'a tcreate reg_spec ~e creates a new state machine where the state is stored in a register created from reg_spec and e.