Configuration for the memory builder. See documentation below for elaboration about the purpose of configuration fields.
type inferred_memory = {rtl_attributes : Hardcaml.Rtl_attribute.t Base.list Base.option;rw_order : [ `Wbr | `Rbw ];}val sexp_of_inferred_memory : inferred_memory -> Sexplib0.Sexp.tval rw_order : inferred_memory -> [ `Wbr | `Rbw ]val rtl_attributes :
inferred_memory ->
Hardcaml.Rtl_attribute.t Base.list Base.optionmodule Fields_of_inferred_memory : sig ... endval sexp_of_how_to_instantiate_ram : how_to_instantiate_ram -> Sexplib0.Sexp.ttype underlying_memory = {data_width : Base.int;cascade_height : Cascade_height.t;how_to_instantiate_ram : how_to_instantiate_ram;}val how_to_instantiate_ram : underlying_memory -> how_to_instantiate_ramval cascade_height : underlying_memory -> Cascade_height.tval data_width : underlying_memory -> Base.intmodule Fields_of_underlying_memory : sig ... endtype t = {underlying_memories : underlying_memory Base.list;underlying_ram_read_latency : Base.int;vertical_dimension : Base.int;horizontal_dimension : Base.int;combinational_output : Base.bool;}val vertical_dimension : t -> Base.intThe size of the outermost inner dimension. ie: shape1
val horizontal_index_width : t -> Base.intThe bit width for the horizontal dimension. Note that this will return 0 when the appropriate dimension is zero.
val vertical_index_width : t -> Base.intSimilar to horizontal_index_width, but for the vertical index
val read_latency : t -> Base.intEquivalent to underlying_ram_read_latency + if combinational_output then 1 else 0
val create_simple_1d_config :
depth:Base.int ->
num_bits_per_entry:Base.int ->
ram_read_latency:Base.int ->
how_to_instantiate_ram:how_to_instantiate_ram ->
tCreate the simplest possible 1D configuration with a single RAM architecture.
module type S = sig ... end