package hardcaml_xilinx

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package hardcaml_xilinx
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val rw_order : (inferred_memory, [ `Wbr | `Rbw ]) Fieldslib.Field.t
val fold : init:'acc__0 -> rtl_attributes: ('acc__0 -> (inferred_memory, Hardcaml.Rtl_attribute.t Base.list Base.option) Fieldslib.Field.t -> 'acc__1) -> rw_order: ('acc__1 -> (inferred_memory, [ `Wbr | `Rbw ]) Fieldslib.Field.t -> 'acc__2) -> 'acc__2
val make_creator : rtl_attributes: ((inferred_memory, Hardcaml.Rtl_attribute.t Base.list Base.option) Fieldslib.Field.t -> 'acc__0 -> ('input__ -> Hardcaml.Rtl_attribute.t Base.list Base.option) * 'acc__1) -> rw_order: ((inferred_memory, [ `Wbr | `Rbw ]) Fieldslib.Field.t -> 'acc__1 -> ('input__ -> [ `Wbr | `Rbw ]) * 'acc__2) -> 'acc__0 -> ('input__ -> inferred_memory) * 'acc__2
val create : rtl_attributes:Hardcaml.Rtl_attribute.t Base.list Base.option -> rw_order:[ `Wbr | `Rbw ] -> inferred_memory
val to_list : rtl_attributes: ((inferred_memory, Hardcaml.Rtl_attribute.t Base.list Base.option) Fieldslib.Field.t -> 'elem__) -> rw_order:((inferred_memory, [ `Wbr | `Rbw ]) Fieldslib.Field.t -> 'elem__) -> 'elem__ Base.list
val map_poly : ([< `Read | `Set_and_create ], inferred_memory, 'x0) Fieldslib.Field.user -> 'x0 Base.list
module Direct : sig ... end