package hardcaml_xilinx

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package hardcaml_xilinx
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val create : ?showahead:Base.bool -> ?build_mode:Hardcaml.Build_mode.t -> ?fifo_memory_type:Hardcaml_xilinx__.Fifo_memory_type.t -> Base.unit -> capacity:Base.int -> read_clock:Hardcaml.Signal.t -> write_clock:Hardcaml.Signal.t -> clear:Hardcaml.Signal.t -> write:Hardcaml.Signal.t -> d:Hardcaml.Signal.t -> read:Hardcaml.Signal.t -> Hardcaml.Signal.t Hardcaml.Fifo.t

Create a synchronous FIFO with the given capacity. If build_mode is Simulation a hardcaml model is generated. Otherwise a XPM primitive FIFO is instantiated.

If the overflow_check (resp underflow_check)) logic is enabled a write will not occur when the fifo is full (resp empty).

showahead reduces the fifo read latency from 1 to 0 cycles relative to rd.

In simulation mode, the write clock is ignored and the FIFO is effectively synchronous.