package hardcaml_xilinx

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package hardcaml_xilinx
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val fold : init:'acc__0 -> data_width: ('acc__0 -> (underlying_memory, Base.int) Fieldslib.Field.t -> 'acc__1) -> cascade_height: ('acc__1 -> (underlying_memory, Cascade_height.t) Fieldslib.Field.t -> 'acc__2) -> how_to_instantiate_ram: ('acc__2 -> (underlying_memory, how_to_instantiate_ram) Fieldslib.Field.t -> 'acc__3) -> 'acc__3
val make_creator : data_width: ((underlying_memory, Base.int) Fieldslib.Field.t -> 'acc__0 -> ('input__ -> Base.int) * 'acc__1) -> cascade_height: ((underlying_memory, Cascade_height.t) Fieldslib.Field.t -> 'acc__1 -> ('input__ -> Cascade_height.t) * 'acc__2) -> how_to_instantiate_ram: ((underlying_memory, how_to_instantiate_ram) Fieldslib.Field.t -> 'acc__2 -> ('input__ -> how_to_instantiate_ram) * 'acc__3) -> 'acc__0 -> ('input__ -> underlying_memory) * 'acc__3
val create : data_width:Base.int -> cascade_height:Cascade_height.t -> how_to_instantiate_ram:how_to_instantiate_ram -> underlying_memory
val to_list : data_width:((underlying_memory, Base.int) Fieldslib.Field.t -> 'elem__) -> cascade_height: ((underlying_memory, Cascade_height.t) Fieldslib.Field.t -> 'elem__) -> how_to_instantiate_ram: ((underlying_memory, how_to_instantiate_ram) Fieldslib.Field.t -> 'elem__) -> 'elem__ Base.list
val map_poly : ([< `Read | `Set_and_create ], underlying_memory, 'x0) Fieldslib.Field.user -> 'x0 Base.list
module Direct : sig ... end