package hardcaml_xilinx

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package hardcaml_xilinx
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val fold : underlying_memory -> init:'acc__0 -> data_width: ('acc__0 -> (underlying_memory, Base.int) Fieldslib.Field.t -> underlying_memory -> Base.int -> 'acc__1) -> cascade_height: ('acc__1 -> (underlying_memory, Cascade_height.t) Fieldslib.Field.t -> underlying_memory -> Cascade_height.t -> 'acc__2) -> how_to_instantiate_ram: ('acc__2 -> (underlying_memory, how_to_instantiate_ram) Fieldslib.Field.t -> underlying_memory -> how_to_instantiate_ram -> 'acc__3) -> 'acc__3
val set_all_mutable_fields : underlying_memory -> Base.unit