package hardcaml_xilinx

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package hardcaml_xilinx
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Module Hardcaml_xilinx.Byte_write_widthSource

Sourcetype t =
  1. | B8
    (*

    byte width of 8 bits

    *)
  2. | B9
    (*

    byte width of 9 bits

    *)
  3. | Full
    (*

    byte width of size of the write data bus

    *)